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Energy Efficient Wireline Communication for High Performance Computing Systems

Release time:November 2, 2018

Topic: Energy Efficient Wireline Communication for High Performance Computing Systems

Speaker: Vasilis F. Pavlidis, The University of Manchester

Time: 10:00-11:30 am, November 6

Venue: Room 425, IRC

Abstract:

The idea of ubiquitous computing with 30 billion connected devices in service by 2020, ranging from micro-scale biomedical implant chips, to portable and wearable electronics, to high performance data centres, has become an ambitious objective of this decade. The major challenge in building such a large and complex ecosystem lies in delivering technologies capable of processing information within the energy budget as small as 20 pJ per operation. This level of energy efficiency is imperative to ensure unaffected battery life in the next generation micro-scale and portable devices as well as to allow high performance computing (HPC) at exascale level within a manageable power budget.

Although computation largely benefits from technology scaling, intra- and inter-die communication becomes increasingly more energy demanding. Based on the trends observed in the past few decades, the energy of computation typically reduces 10× every 5 years, while the energy of data communication reduces only 2.4× during the same time period. This leads to an imminent power crisis where the energy of communication dominates the total power budget of an integrated system inhibiting further performance growth unless new mechanisms of energy efficient data transfer become available.

This presentation aims to show our latest research findings addressing the problem of energy efficient inter-chip communication for HPC applications where the dissipated power becomes a dominant factor limiting performance. In the first part of the talk, I will discuss a transceiver for inter-chip (inter-tier) communication, fabricated in a 28 nm FDSOI technology designed as a part of the Horizon 2020 Research Programme ExaNoDe project. In the second part, I will present a novel signal encoding technique that improves energy efficiency for chip-to-chip communication.

Short Biography:

Vasilis F. Pavlidis is an Associate Professor in the School of Computer Science at the University of Manchester, UK. He holds an MSc and PhD degree from the University of Rochester, Rochester, NY, obtained in 2003 and 2008, respectively, all in Electrical and Computer Engineering. From 2008 to 2012, he was a post-doctoral researcher at the Integrated Systems Laboratory of EPFL, Switzerland. His research interests are in the area of interconnect modeling and analysis, 3D integration, and other issues related to VLSI design. He is the leading author of the book Three-Dimensional Integrated Circuit Design, (1st and 2nd Editions), also translated in Chinese, and contributor to the software tool, Manchester Thermal Analyzer.

 

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