Topic: Just Change the Instruction Set: Diversity as a Lever for Better Security, Performance and Efficiency in General Purpose Computing
Speaker: Dean Tullsen, University of California, San Diego
Date: August 20, 10:00 AM
Venue: G849, New Main Building
Prior research has shown that single-ISA (instruction set architecture) heterogeneous chip multiprocessors have the potential for greater performance and energy efficiency than homogeneous CMPs. However, restricting the cores to a single ISA removes an important opportunity for greater heterogeneity. This talk will introduce heterogeneous-ISA multicore processors. Enabling such an architecture introduces significant compilation and architectural challenges, which we'll discuss. This enables the design of an architecture that has the potential to outperform the best single-ISA heterogeneous architecture by as much as 21%, with 23% energy savings and a reduction of 32% in Energy Delay Product. Further, we’ll show that this architecture also enables enhanced security -- in particular, thwarting Return-Oriented Programming attacks. Last, we'll show that the benefits of heterogeneous ISAs can be achieved with a novel approach called composite-ISAs, which achieve ISA diversity by constructing subsets of a single superset ISA, bypassing most of the most significant barriers to adoption of heterogeneous ISAs.
Biography of the Speaker:
Dean Tullsen is a professor and chair of the computer science and engineering department at University of California, San Diego. He received his Ph.D. from the University of Washington in 1996, where he introduced simultaneous multithreading (hyper-threading). He has continued to work in the area of computer architecture and back-end compilation, where with various co-authors he has introduced many new ideas to the research community, including threaded multipath execution, symbiotic job scheduling for multithreaded processors, dynamic critical path prediction, speculative precomputation, heterogeneous multi-core architectures, conjoined core architectures, event-driven simultaneous code optimization, and data triggered threads. He is a Fellow of the ACM and the IEEE. He has twice won the Influential ISCA Paper Award. He is a former chair of the IEEE Technical Committee on Computer Architecture.
School of Computer Science and Engineering