Recently, the research team led by Professor Zhao Weisheng from the School of Integrated Circuit Science and Engineering has achieved a major breakthrough in spin-based chip technology. The related work, titled "An Ising machine for combinatorial optimization based on sub-nanosecond CMOS-integrated magnetoresistive random-access memory," has been published online in Nature Electronics, a renowned international academic journal. This marks the team's fifth paper in Nature Electronics.

The team has developed a 96-kb voltage-controlled magnetoresistive random-access memory (VC-MRAM) based on a 40-nanometer CMOS process, constructing an ultrafast, low-power Ising machine with sub-nanosecond probabilistic switching. Chip measurement and verification have been completed for industrial-grade EDA combinatorial optimization tasks. The energy consumption for a single spin update of the device is less than 40 fJ, and the system energy efficiency reaches 1.92×10⁵ solutions/s/W, surpassing state-of-the-art Ising machines by 60–18,000 times. 

Fig. 1 Overview of voltage-controlled spintronic Ising machine (VSIM)

Research Background: Challenges in Solving NP-hard Problems

NP-hard combinatorial optimization problems are widely found in artificial intelligence, materials science, finance, transportation, communications and integrated circuit design. A large number of real-world problems boil down to "finding the optimal solution among exponentially numerous candidate options". As problem scales expand and intelligent systems demand real-time prediction and autonomous decision-making, the traditional von Neumann architecture faces multiple challenges in computing speed and capacity.

As a hot research topic in recent years, the Ising machine offers a physics-inspired computing paradigm: optimization problems are mapped to the energy function of a spin system, and the system spontaneously evolves to the ground state with the lowest energy via spin dynamics to search for the global optimum. Ising machines are promising as dedicated coprocessors for existing computing systems, assisting high-performance computing in data centers, edge intelligent platforms and space computing scenarios. Quantum processors, photonic Ising machines and conventional CMOS technologies are under rapid development. Nevertheless, converting the solving potential of physical evolution into deployable computing capability still requires simultaneous breakthroughs in key aspects including solution quality, operating speed, system energy efficiency and scalability.

Key Breakthrough: Enabling Sub-nanosecond Probabilistic Bits with Magnetic Tunnel Junctions

The stochastic nature of magnetization switching in magnetic tunnel junctions (MTJs) makes them ideal candidates for implementing Ising spins. However, previous schemes based on superparamagnetic tunnel junctions (SMTJs) and spin-orbit torque magnetic tunnel junctions (SOT-MTJs) are mostly current-driven, suffering from slow write operations, high power consumption and validation primarily on discrete devices, which limits the potential of chip-level integration.

The research team adopted an alternative approach by exploiting the voltage-controlled magnetic anisotropy (VCMA) effect. Voltage directly modulates the magnetic anisotropy barrier, enabling a single spin update within 0.3 to 1 nanosecond with energy consumption below 40 fJ. By precisely tuning the on-chip write pulse width, the single-pulse switching probability can be continuously adjusted from 0 to 100%, realizing in-situ probabilistic updates of Ising spins.

Fig. 2 Implementation of Ising spins using VCMA-MTJ with tunable switching probability

On-chip Integration: An Ising computing network supporting 96,000 nodes

Building on the device breakthrough, the team collaborated with Suzhou Inston Technology Co. Ltd. to fabricate a 96-kb VC-MRAM chip using the 40-nm CMOS process. The on-chip magnetic tunnel junctions have a diameter of approximately 70 nanometers. An on-chip pulse generator with pulse width tuning precision at the ten-picosecond level was designed and integrated to implement on-chip Ising spin updates and break the read-write bandwidth bottleneck. Combined with an FPGA-based programmable system, a closed-loop computing workflow covering problem mapping, spin update and ground-state solution is realized.

Performance evaluation shows the system achieves an energy efficiency of 1.92×10⁵ solutions/s/W. Compared with GPUs, quantum processors and other computing implementations based on photonic devices, phase-change nano-oscillators and memristors, the system energy efficiency is improved by 60 to 18,000 times.

Fig. 3 Implementation of VSIM with the 96-kb VC-MRAM chip

Application Validation: Real-time Computing for EDA Routing Problems

The team applied the spin Ising machine to two typical NP-hard combinatorial optimization problems in integrated circuit design—global routing and layer assignment. The objective of wirelength minimization and routing connectivity constraints were mapped to the Ising model, and real-time high-efficiency solving was demonstrated on the chip system. Experiments show that the system Hamiltonian converges rapidly to the ground state and outputs high-quality routing schemes, demonstrating the potential of spin Ising chips for industrial-grade EDA applications.

This work not only proposes a new physical implementation of Ising machines and provides new insights to address the speed and energy efficiency bottlenecks hindering practical Ising machines, but also opens a technical route for new computing chips centered on a probabilistic intelligent paradigm.

Fig. 4 Global routing demonstration on VSIM

Authors and Affiliations

Beihang University is the first affiliation. Associate Professor Li Sai and PhD student Zhang Yihao from the School of Integrated Circuit Science and Engineering are co-first authors; Professor Zhao Weisheng serves as the corresponding author. 

The work is a collaborative effort by the School of Integrated Circuit Science and Engineering of Beihang University, the National Key Laboratory of Spintronic Chip and Technology, Hangzhou International Innovation Institute of Beihang University, Shandong Laboratory of ASIC and Intelligent Instruments in Qingdao and Suzhou Inston Technology Co. Ltd. Professor Zeng Lang, Professor Wang Peng from the School of Integrated Circuit Science and Engineering, Dr. Albert Lee and Dr. Wu Di from Suzhou Inston Technology Co. Ltd., and Dr. Zhu Zheng from Xunliang Technology participated in the research. 

This work was supported by the National Natural Science Foundation of China, the Beijing Natural Science Foundation, the Young Elite Scientists Sponsorship Program of the Beijing High Innovation Plan, the XPLORER PRIZE, the Beijing Outstanding Young Scientist Program, and the Fundamental Research Funds for the Central Universities, among other research grants and talent programs.

Professor Zhao Weisheng's research group has long been dedicated to ultra-high-speed and ultra-low-power spin devices and chips. The team continuously produces high-impact results in top international journals and conferences including Nature Electronics, Nature Communications, Science Advances, PNAS and IEDM, establishing a complete innovation chain spanning fundamental research to application validation in spin chip technology.

Article link: https://www.nature.com/articles/s41928-026-01700-6

Editor: Liu Tingting